Resistance-switching oxide thin film devices

ABSTRACT

Resistance-switching oxide films, and devices therewith, are disclosed. Resistance-switching oxide films, according to certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix and dopant are preferably in solid solution. The insulator oxide matrix may also preferably include about 6 to about 12 atomic percent of a conducting material dopant. According to certain aspects of the present invention, the insulator oxide matrix, the conducting material dopant, or both, may have a perovskite crystal structure. The insulator oxide matrix may preferably include at least one of LaAlO 3  and CaZrO 3 . Preferred conducting material dopants include SrRuO 3 , CaRuO 3 , or combinations thereof.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 11/291,945 filed Nov. 30, 2005, the entirety of which is incorporated by reference herein.

FIELD OF THE INVENTION

The invention generally relates to semiconductor devices, and more particularly to resistance-switching oxide semiconductor devices. The present invention also generally relates to resistance-switching oxide compositions and methods for making same.

BACKGROUND OF THE INVENTION

Materials exhibiting reversible resistance switching are attractive for many of today's semiconductor devices, including non-volatile random-access memory devices. However, previous efforts in the art to reversibly vary electrical performance have exhibited numerous drawbacks. For example, some capacitance-switching semiconductor devices, such as doped Schottky-junction diodes, require relatively large amounts of electrical power (voltage) to switch to, and maintain, a particular capacitance state. Still further, such a device completely loses its capacitance state when the power is withdrawn. Current leakage, and associated heat-build up, are also especially problematic with these switchable semiconductor devices. Thus, high power consumption, current leakage and poor retention characteristics make these devices unsuitable for many practical applications.

Other efforts in the art have taught that several different resistance-switching technologies can be triggered by voltage. This phenomenon has sometimes been called an EPIR (Electrical Pulse Induced Resistance) switching effect. EPIR semiconductor devices are disclosed in U.S. Pat. No. 3,886,577 (Buckley). In the Buckley devices, a sufficiently high voltage (50 V) is applied to a semiconductor thin film in which an approximately 10 micron portion, or filament, of the film may be set to a low resistivity state. Filament size is highly dependant on the amount of current flowing through the device. The device may then be reset to a high resistance state by the action of a second high current pulse (150 mA). However, the set voltage is strongly affected by the number of switching cycles performed. Thus, these devices generally exhibit high power consumption and poor cycle fatigue performance.

Recent efforts in the art have investigated ferroelectric and magnetoresistive materials for non-volatile memory applications. These materials, however, suffer from cycle fatigue and retention problems. Moreover, many magnetoresistive oxide devices require magnetic switching fields and have low operating temperatures.

Some thin film materials in the perovskite family, especially in colossal magnetoresistive (CMR) thin films, have exhibited reversible resistance changes upon application of an electrical stimuli in a magnetic field. It has been recently found that some transition metal oxides in the perovskite family exhibit resistance-switching under a voltage trigger in the absence of a magnetic field. Indeed, the recent observation of the electrical pulse induced resistance (EPIR) change effect in perovskite oxide thin films at room temperature and in the absence of a magnetic field has drawn much attention. See, e.g., “Electric-Pulse Induced Reversible Resistance Change Effect in Magnetoresistive Films,” S. Q. Liu, N. J. Wu, A. Ignatiev, Applied Physics Letters, Vol. 76, No. 23 (2000). In these previous efforts, a Pr_(1-x)Ca_(x)MnO₃ (PCMO) oxide film placed between two electrodes served as an EPIR device. The resistance states of such simple structured semiconductor devices were switchable by the application of a voltage trigger. The trigger could directly increase or decrease the resistance of the thin film sample depending on voltage polarity. Such voltage triggering phenomenon can be useful in a variety of device applications, including non-volatile memory devices such as resistance random access memory (RRAM) devices.

These early devices, however, required relatively high voltage triggers and the EPIR effect was found to be cycle dependant. The EPIR effect, measured as the ratio between the resistance states, was found to decrease as the number of triggering events increased. Thus, the high power requirements and lack of resistance state stability plagued these early EPIR compositions and devices. Although, the basic mechanism responsible for the EPIR effect is still under investigation, there exist a need in the art to develop improved resistance-switching semiconductor devices for potential application in different technology areas.

Thus, there is a need in the art for resistance-switching semiconductor devices having low power consumption. Still further, there is a need in the art for such semiconductor devices having low voltage leakage and high retention of the respective low and high resistance states. There is also a need in the art for resistance-switching semiconductor devices having improved cycle fatigue performance.

SUMMARY OF THE INVENTION

Resistance-switching oxide films, according to the certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix and dopant are preferably in solid solution. The insulator oxide matrix may thus preferably include about 5 to about 17 atomic percent of a conducting material dopant. Most preferably, the insulator oxide matrix may include about 6 to about 12 atomic percent of a conducting material dopant. The insulator oxide matrix may include MgO, while the dopant may include Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiO, VO, MnO, FeO, CoO, NiO, CuO, or combinations thereof.

More preferably, at least one of the insulator oxide matrix and the conducting material matrix may have a perovskite crystal structure. As used herein, perovskite crystal structures may also include perovskite-like crystal structures. In this regard, the preferred insulator oxide matrix may include LaAlO₃, CaZrO₃, SrZrO₃, BaZrO₃, CaHfO₃, SrHfO₃, BaHfO₃, LaScO₃, GdScO₃, DyScO₃, or combinations thereof. Preferred conducting material dopants include SrRuO₃, CaRuO₃, BaRuO₃, SrMoO₃, CaMoO₃, BaMoO₃, SrIrO₃, CaIrO₃, BaIrO₃, SrVO₃, CaVO₃, SrNbO₃, CaNbO₃, SrCrO₃, SrFeO₃, CaFeO₃, LaTiO₃, LaNiO₃, LaCuO₃, LaRhO₃, (La,Sr)TiO₃, (La,Sr)FeO₃, (La,Sr)MnO₃, or combinations thereof.

Certain presently preferred embodiments of the present invention include semiconductor devices having at least one resistance-switching oxide film as described herein. In accordance with an embodiment of the present invention, the device may include a substrate, a first electrically conductive layer disposed on the substrate, at least one resistance-switching oxide film, as described herein, disposed on the first conductive layer, and a second electrically conductive layer disposed on the oxide film. According to certain preferred aspects of the present invention, the first electrically conductive layer may serve as the device substrate. The first electrically conductive layer and resistance-switching oxide layer may also be deposited to maintain epitaxial registry with a single crystal semiconductor substrate. In accordance with still other embodiments of the present invention, the semiconductor device may include at least one resistance-switching oxide film wherein the dopant has a work function equivalent to that of the first electrically conductive layer, the second electrically conductive layer, or both.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects of the present invention will become more apparent in reference to the accompanying drawings in which:

FIG. 1( a)-1(c) depict various embodiments of semiconductor devices according to certain preferred aspects of the present invention.

FIG. 2 illustrates the voltage cycle applied at room temperature to certain preferred embodiments of the present invention.

FIG. 3 shows the surface topography of a SrRuO₃ (SRO) first conductive layer deposited under preferred pulsed laser deposition (PLD) conditions.

FIG. 4 illustrates the low resistivity of a SrRuO₃ (SRO) first conductive layer on a SiTiO₃ (STO) substrate layer deposited under preferred PLD conditions.

FIG. 5 is an X-ray diffraction spectrograph of a SrRuO₃ (SRO) first conductive layer deposited under preferred PLD conditions.

FIG. 6 shows the surface topography of a LaAlO₃:SrRuO₃ (LAO:SRO) layer using preferred PLD techniques at 500° C. and PO₂=1 mTorr.

FIG. 7 shows an X-ray diffraction spectrograph of a preferable strain-relaxed LaAlO₃:SrRuO₃ (LAO:SRO) film as disposed on a SrTiO₃ (STO) substrate.

FIG. 8 depicts the surface topographies of LaAlO₃:SrRuO₃ (LAO:SRO) layers deposited at various temperatures.

FIG. 9 shows the effect of PLD deposition conditions on resistance-switching of a LaAlO₃:SrRuO₃ (LAO: SRO) layer. Generally, higher PLD deposition temperatures resulted in greater surface roughness. Still further, greater oxygen partial pressure also resulted in greater surface roughness. Films with greater surface roughness showed generally non-uniform resistance-switching.

FIG. 10 depicts the resistance-switching performance of LaAlO₃:SrRuO₃ (LAO:SRO) films. Preferred resistance-switching performance may be obtained with about 6 to about 12 atomic percent SrRuO₃.

FIG. 11 shows the I-V/R-V plot for a preferred semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃.

FIG. 12 shows the I-V/R-V plot for a preferred semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 6 atomic percent SrRuO₃.

FIG. 13 shows the I-V/R-V plot for a preferred semiconductor device having a CaZrO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃.

FIG. 14 shows that certain preferred semiconductor devices according to certain preferred aspects of the present invention have a lower initial resistance and switch to higher resistance at about 2 V, and switched back to low resistance at opposite bias at about −1 V. The semiconductor device comprised a LaAlO₃:SrRuO₃ resistance-switching layer with about 11 atomic percent SrRuO₃

FIG. 15 shows that certain preferred semiconductor devices according to certain preferred aspects of the present invention have a lower initial resistance and switch to higher resistance at about 2 V, and switch back to low resistance at opposite bias at about −1 V. The semiconductor device comprised a CaZrO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃

FIG. 16 shows the retention of low/high resistances obtained by preferred semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃.

FIG. 17 illustrates the switching cycle performance of a semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 6 atomic percent SrRuO₃. The device showed little appreciable performance degradation over several thousand switching cycles.

FIG. 18 shows the capacitance performance of a semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 6 atomic percent SrRuO₃.

FIG. 19 depicts a schematic representation of electrical properties of a device according to certain preferred aspects of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention relates to two-point resistance-switching oxide layers, semiconductor devices incorporating same, and methods for making such oxide layers and devices. Resistance-switching oxide layers, and devices incorporating same, are suitable for various non-volatile memory applications. Under a resistance-switching regime, when an appropriate voltage pulse is applied, the resistance of the oxide layer can be increased and remain so until application of another appropriate voltage pulse, typically of the opposite polarity, which returns the resistance to the low value. Devices incorporating such resistance-switching oxide layers should be switchable at a modest voltage, preferably below about 3 V.

Resistance-switching oxide films, according to the certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix (solvent) and dopant (solute) are preferably in solid solution, without appreciable precipitate formation or phase separation. The insulator oxide matrix may preferably include about 5 to about 17 atomic percent of a conducting material dopant. Most preferably, the insulator oxide matrix may include about 6 to about 12 atomic percent of a conducting material dopant. The insulator oxide matrix may include MgO. The insulator oxide may also include at least one binary oxide, including but not limited to:

-   -   (a) X₂O₃ where X is Al, Ga, In, Sc, Y, Gd, Tb, Dy, Ho, Er, Tm,         Yb, or Lu;     -   (b) X₁O₂ where X₁ is Si, Ge, Zr or Hf, and     -   (c) X₂O₅ where X is Nb or Ta.

Dopants may include various metals and/or their respective oxides such as Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiO, VO, MnO, FeO, CoO, NiO, CuO, or combinations thereof. Dopants may also include Pt, Pd, Au, Ag, Ir, Rh, Os, Ru, Re, W, Mo, Ta, Nb, Hf, Zr, Al, or combinations thereof. Dopants may further include VO₂, CrO₂, NbO₂, MoO₂, RuO₂, RhO₂, WO₂, OSO₂, IrO₂, PtO₂, or combinations thereof.

More preferably, at least one of the insulator oxide matrix and the conducting material matrix may have a perovskite, or perovskite-like, crystal structure. In this regard, the preferred insulator oxide matrix may include CaZrO₃, SrZrO₃, BaZrO₃, or combinations thereof. The insulator oxide matrix may also include at least one of:

-   -   (a) X₁HfO₃, where X₁ is Ca, Sr, or Ba;     -   (b) X₁AlO₃, where X₁ is La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy,         Ho, Er, Tm, Yb, Lu, or Y;     -   (c) X₁ScO₃, where X₁ is La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy,         Ho, Er, Tm, Yb, Lu, or Y; and     -   (d) Ba(X₁)_(1/3)(X₂)_(2/3)O₃, where X₁ is Mg or Zn, and X₂ is Nb         or Ta.

Preferred conducting oxide dopants include perovskite structures including, but not limited to, SrRuO₃, CaRuO₃, BaRuO₃, SrMoO₃, CaMoO₃, BaMoO₃, SrIrO₃, CaIrO₃, BaIrO₃, SrVO₃, CaVO₃, SrNbO₃, CaNbO₃, SrCrO₃, SrFeO₃, CaFeO₃, LaTiO₃, LaNiO₃ LaCuO₃, LaRhO₃, (La,Sr)TiO₃, (La,Sr)MnO₃, (La,Sr)FeO₃, or combinations thereof. Dopants may also include at least one of:

-   -   (a) A₁X₁O₃, where A₁ is Ca, Sr, or Ba; and X₁ is V, Cr, Mn, Fe,         Co, Nb, Mo, Ru, Rh, Ta, W, Re, Os, or Ir;     -   (b) A₁X₁O₃ where A₁ is La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy,         Ho, Er, Tm, Yb, Lu, or Y; and X₁ is Ti, V, Co, Ni, Cu, Nb, Mo,         Ru, Rh, or Ir; and     -   (c) (A₁,A₂)X₁O₃ where A₁ is La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb,         Dy, Ho, Er, Tm, Yb, Lu, or Y; A₂ is Ca, Sr, or Ba; and X₁ is Ti,         V, Cr, Mn, Fe, Co, Ni, Cu, Nb, Mo, Ru, Rh, Ta, W, Re, Os, or Ir.

Certain presently preferred embodiments of the present invention also include semiconductor devices having at least one resistance-switching oxide layer as described herein. In accordance with an embodiment of the present invention, the device may include a substrate, a first conductive layer disposed on the substrate, at least one resistance-switching oxide layer as described herein, and a second electrically conductive layer disposed on the oxide layer. The first and second electrically conductive layers may respectively serve as bottom and top electrodes. In this regard, at least one of the electrodes may also comprise Pt, Pd, Ni, Au, Ag, Cu, Ir, Rh, Co, Os, Ru, Fe, Re, Mn, W, Mo, Cr, Ta, Nb, V, Hf, Zr, Ti, Al, doped Si, metal silicides, or combinations thereof. Electrodes may also comprise CrO₂, MoO₂, RuO₂, RhO₂, WO₂, OSO₂, IrO₂, PtO₂, or combinations thereof. In certain preferred embodiments, the first electrically conductive layer may also serve as the device substrate. In still other preferred embodiments, the semiconductor device may include at least one resistance-switching oxide film wherein the dopant has a work function equivalent to that of the first electrically conductive layer, the second electrically conductive layer, or both. Persons skilled in the art understand the concept of work function, and further reference may be made to CRC Handbook of Chemistry and Physics, 83^(rd) ed., Lide, D. R (ed.), p. 12-130, CRC Press (2002), hereby incorporated by reference. As used herein, a work function may be considered equivalent if it is within about 25% of at least one target comparative work function value.

The various layers may be deposited by any number of sputtering and/or deposition techniques including, but not limited to, direct-current (DC) sputtering, radio-frequency (RF) sputtering, pulsed laser deposition (PLD), physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), and ion-assisted deposition (IAD). The electrically conductive layer may be preferably deposited using a shadow mask technique in conjunction with RF sputtering. In accordance with certain preferred aspects of the present invention, the first electrically conductive layer and resistance-switching oxide layer may be deposited to maintain epitaxial registry, i.e., lattice matching, with a single crystal substrate. As seen in FIG. 1( a), the device may have a SrTiO₃ single crystal substrate in the 100 orientation, SrRuO₃ as the first electrically conductive layer/bottom electrode, and platinum as the second electrically conductive layer/top electrode. The device may further include a resistance-switching oxide layer having LaAlO₃ as the insulator oxide matrix and SrRuO₃ as the conducting material dopant. Preferably, SrRuO₃ is present in an amount of about 6 to about 12 atomic percent. FIG. 1( b) shows an alternate embodiment of the present invention wherein the resistance-switching oxide layer comprises a CaZrO₃ insulator matrix doped with SrRuO₃.

At least one isolation layer may be included to alter the low voltage performance of the semiconductor device. FIG. 1( c) depicts yet another embodiment of the present invention having a LaAlO₃ isolation layer disposed between the resistance-switching layer and the respective top and bottom electrodes. Here again, LaAlO₃ is shown as the insulator oxide matrix and SrRuO₃ as the conducting dopant. In accordance with certain preferred aspects of the present invention, at least one of the isolation layers may be composed of the same insulator oxide utilized in the resistance-switching layer. Room temperature resistance-switching characteristics, depicted as I-V and R-V plots, of certain preferred embodiments of the present invention were determined utilizing a full cycle of positive and negative voltage pulse ranges as shown in FIG. 2.

FIG. 3 shows the surface topography of a SrRuO₃ first conductive layer deposited under preferred PLD conditions. Smooth high quality layers were deposited at 700° C., 200 mJ, 2 Hz and PO₂ of 100 mTorr using a PLD method. As shown in FIG. 4, step-flow layers deposited under high oxygen partial pressure conditions generally exhibited preferably low initial resistivity. Post-deposition, these films were annealed in-situ at 500° C. at a PO₂ of 300 Torr for about 1 hour. FIG. 5 shows an X-ray diffraction spectrograph of a SrRuO₃ (SRO) strain relaxed film as disposed on an SiTiO₃ (STO) substrate.

FIG. 6 shows the surface topography of a LaAlO₃:SrRuO₃ (LAO:SRO) layer deposited using preferred PLD techniques at 500° C. and PO₂ of about 1 mTorr. Per layer growth rates were about 0.0083 nm/laser-shot for LAO as compared to about 0.0084 nm/laser-shot for SRO. FIG. 7 shows an X-ray diffraction spectrograph of a preferable strain-relaxed LAO:SRO film as disposed on an STO substrate. FIG. 8 depicts the varied surface topographies of LaAlO₃:SrRuO₃ (LAO:SRO) layers deposited at the preferred partial pressure but assorted temperatures. Generally, at a PO₂ of about 1 mTorr, higher PLD deposition temperatures resulted in greater surface roughness. FIG. 9 shows the effect of PLD conditions on resistance-switching of LaAlO₃:SrRuO₃ (LAO:SRO) layers. Those films deposited at higher temperatures, higher partial oxygen pressure, or both, commonly resulted in greater surface roughness. Films with greater surface roughness generally showed poor resistance-switching performance.

FIG. 10 depicts the resistance-switching performance of LaAlO₃:SrRuO₃ (LAO:SRO) films. The LAO:SRO general electrical characteristic may be adjusted from insulating to conducting by changing the SRO content from about 2 to about 17 atomic percent. Preferred resistance-switching performance could be obtained with about 6 to about 12 atomic percent SRO. Indeed, FIGS. 10( b) and 10(c) show exemplary resistance-switching characteristics of the present invention at SrRuO₃ contents of about 10 atomic percent and about 6 atomic percent, respectively. FIGS. 10( a) and 10(d) comparatively show the general electrical characteristics of respective typical un-doped SRO and LAO films. FIG. 11 shows the I-V plot for a preferred semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃. At this SrRuO₃ content, the device shows a preferred hysteric resistance response to applied voltage. It should be noted that the baseline resistance, of about 300Ω, for the SrRuO₃ first conductive layer (bottom electrode) is relatively high but does not adversely affect the overall resistance-switching performance of the device. FIG. 12 shows the I-V plot for a preferred semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 6 atomic percent SrRuO₃. Although the device exhibits a higher initial resistance, it also exhibits a hysteresis response to the applied voltage cycle. FIG. 13 shows a similar hysteresis effect for a preferred semiconductor device having a CaZrO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃.

As shown in FIGS. 10-13, the applied voltage cycle results in high initial current indicating a relatively low resistance. For a LaAlO₃:SrRuO₃ (LAO:SRO) resistance-switching layer, an abrupt change in slope then occurs at a large positive voltage indicating a switch to high resistance. For a CaZrO₃:SrRuO₃ (CZO:SRO) resistance-switching layer, this change also appears to occur at large positive voltage. This characteristic switching from low to high resistance indicates that the switching does not involve a filamentary mechanism in which an initially high resistance state transitions to a low resistance state after preferred conducting paths (filaments) are formed at a threshold voltage. Indeed, characteristic filament formation necessarily results in transition from high to low resistance rather than vice-versa.

In accordance with the present invention, the low or high resistance state persists as the magnitude of the voltage continues to increase in the same bias. The resistance state then switches when an appropriately large voltage is applied having an opposite bias. In this regard, a LAO:SRO oxide layer switches to a low resistance state, evidenced as high current on the I-V plot, as the reverse voltage reaches a large negative magnitude. Accordingly, a CZO:SRO oxide layer also switches to a low resistance state when the reverse voltage reaches a large negative magnitude. It is noted that the I-V and R-V response curves are similar among the various insulator matrix compositions and dopant concentrations, thus each showing some degree of current hysteresis and preferred resistance response. Still further, the hysteresis response is largely independent of starting voltage bias. Each insulator:dopant system will thus exhibit the same respective I-V and R-V response regardless of whether the initial voltage bias is positive or negative. Aspects of the current invention include compositional and deposition variations which result in devices having relatively low initial resistance wherein switching-to-high-resistance occurs at negative voltage of appropriate magnitude and switching-to-low-resistance occurs at a positive voltage of appropriate magnitude. And again, these devices would also have the same respective I-V and R-V responses whether the initial voltage is positive or negative.

Devices according to certain preferred aspects of the present invention may be particularly suited for random access memory (RAM) applications. For example, simple two-point resistance devices may be produced to read and write binary information. Thus, a first pulse would set the device to a first resistance state, i.e., a “0” state. The application of a second pulse, of opposite polarity would set the device to a second resistance state, i.e., a “1” state. In this manner, information can be “written” to the device upon the application of a voltage having the appropriate magnitude and polarity. The device may be “read” by applying a voltage pulse of lesser magnitude than the write pulse.

FIG. 14 shows that semiconductor devices according to certain preferred aspects of the present invention having a low initial resistance and switch to higher resistance (write “1” state) at about 2 V, and switch back to low resistance (write “0” state) at an opposite bias of about −1 V. The device may be read at any intermediate voltage, for example 0.5 V. Thus, these devices have modest power consumption and would be particularly suited for micro-sized, or nano-sized, electronic devices. This device included a LaAlO₃:SrRuO₃ resistance-switching layer with about 11 atomic percent SrRuO₃ and a SrRuO₃ first conductive layer/bottom electrode. The resistance layer was deposited using a PLD method at about 700° C. and PO₂ of about 1 mTorr. Surface roughness was measured to be about 0.4 nm. Platinum was deposited as the second conductive layer/top electrode. FIG. 15 depicts the R-V for another device according to certain preferred aspects of the present invention. This device comprised a CaZrO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃. The resistance-switching layer was deposited on a SrRuO₃ first conductive layer/bottom electrode using a PLD method at 600° C. and PO₂ of 10⁻⁶ Torr. Surface roughness was measured to be about 0.5 nm. Platinum was deposited as the second conductive layer/top electrode. The device shows a low initial resistance while switching to a high resistance state (write “1” state) at about 2 V and switching back to a low resistance at about −1 V. This device may be read at any intermediate voltage, for example 0.5 V.

FIG. 16 shows the retention of low/high resistances obtained by a preferred semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 10 atomic percent SrRuO₃. The resistance-switching layer was deposited on a SrRuO₃ first conductive layer/bottom electrode with Pt being the second conductive layer/top electrode. The resistance-switching layer was deposited at about 600° C. and PO₂ of about 100 mTorr using a PLD method. Surface roughness was measured to be about 0.37 nm, and the switching voltage was about 2V (−2V). Here, the device showed excellent retention of the low and high resistance states over the course of several days. FIG. 17 illustrates the switching cycle performance of a semiconductor device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 6 atomic percent SrRuO₃. The resistance-switching layer was deposited at about 500° C. and PO₂ of about 1 mTorr. Sample surface roughness was measured to be about 0.34 nm, and the switching voltage was about 2 V (−2 V). Here, the device showed little appreciable switching performance degradation over several thousand switching cycles. FIG. 18 shows the capacitance variance at the high and low resistance states of a preferred device having a LaAlO₃:SrRuO₃ resistance-switching layer with about 11 atomic percent SrRuO₃. Here, the device was first set to either its high or low resistance state by the appropriate voltage pulse, and the capacitance was measured at 1 MHz. The capacitance at the high resistance state is approximate to that expected for a device having an un-doped LaAlO₃ active layer. At the low resistance state, however, the device exhibits about a fourfold increase in capacitance. Thus, the resistance states can be easily distinguished, and a device may be easily read, using a capacitance measurement method.

If one or more isolation layers are present, then an initial non-zero voltage is needed to transfer current across the isolation and resistance-switching layers, hence a higher resistance would be expected at the zero-voltage state. The inclusion of an isolation layer may thus alter the zero-voltage resistance value, but is not expected to change the overall “shape” of the R-V response curve. Such a device, may also have improved leakage characteristics (i.e., reduced leakage) and may have further improved retention of the read:write states.

Perovskite material systems have traditionally been used for capacitors, dielectrics, piezoelectrics, pyroelectric, and other related applications. In such applications, it is advantageous to have very low conductivity, i.e., very high resistivity, to minimize dielectric loss and/or leakage of stored charge. Perovskite compositions for such applications generally avoid conducting dopants. In those circumstances where dopants are used, a relatively small amount (typically less than about 2 atomic percent) is used to compensate for valence mismatch in the insulator matrix, for example a small amount of Nb⁵⁺ can be used to compensate for the small amount of Ti³⁺ in BaTiO₃. Perovskite material systems may also be used for conductors, electrodes, and other related applications. In these applications, however, very high conductivity, i.e., very low resistivity, is desired to minimize ohmic loss and power consumption. Therefore, the preferred compositions generally include a very high amount of conducting components (typically greater than about 70 atomic percent). Prior efforts in the art have thus taught either very highly-doped or minimally-doped perovskite materials systems for various technological applications. Here, the inventors have surprisingly found a significant and reproducible resistance-switching phenomenon upon mid-range doping of some perovskite material systems.

In regard to a presently preferred embodiment, and without being limited by theory, it is believed that Ru ions (conducting dopant) in the LaAlO₃:SrRuO₃ resistance-switching layer form isolated Ru conductive states separated by LaAlO₃ insulating barriers. Although these electron states are initially empty, under an external bias, electrons may tunnel across a series of LaAlO₃ (insulating matrix) barriers between these empty states to deliver a tunneling current at low resistance. FIG. 19 depicts the theorized manner in which current is believed to be transferred by the action of tunneling electrons. Initially, Ru ions having an energy, e.g., work function, similar to at least one of the first conductive layer and second conductive layer are available for tunneling electron transport. Thus, initial current is high and resistance is low due to the well-matched dopant:conductive layer electron energies. As current proceeds, and some tunneling electrons are trapped at the Ru sites, initially well-matched Ru electron states are filled and no longer available for electron transport. Resistance then increases, and current decreases, as electron transport must proceed via higher energy Ru states which are not as well-matched to the conductive layer(s). Thus, the device is switched to a high resistance state. When the voltage bias is reversed, the trapped electrons are released and the Ru states are again available for transport. Current thus increases and the device is switched back to a low resistance state.

The insulator oxide matrix of the resistance-switching layer should be a good insulator, having high breakdown field, and low conductivity in the desired temperature range of application. Still further, insulator oxide compositions in which cations may exist in more than one valence state, i.e., mixed valence compositions, should be avoided. These features prevent premature breakdown, and the formation of conducting paths due to “forming” or filamentary procedure wherein the application of a large voltage resulting in certain isolated preferred conducting paths in an initially highly electrically resistive material. See J. G. Simmons and R R Verdeber, Proc. R. Soc. London, Ser. A 301, 77 (1968). Here, preferred conducting oxide dopants typically contain cations that exist in more than one valence state. More generally, according to the present invention, dopant content is usually at a low enough concentration such that electron tunneling is the preferred conduction mechanism. At relatively high concentrations, however, “forming” or other conduction mechanisms may predominate. This tunneling threshold concentration may vary due to several factors including, but not limited to, layer thickness and spatial distribution of the conducting dopant. Thus, for example, the threshold concentration for thick films may be greater than that for relatively thin films.

In this manner, tunneling electrons in a insulator matrix:conducting dopant system may effect beneficial resistance-switching characteristics. Certain embodiments of the present invention are particularly advantageous in that high voltage “forming” or filamentary conduction is avoided and resistance-switching may occur at relatively low voltages, typically about 2 V (or about −2 V). Thus, these devices have modest power consumption and would be particularly suited for micro-sized, or nano-sized, semiconductor devices. Low/high resistance states of certain preferred oxide layers, and devices therewith, are remarkably stable while further exhibiting excellent retention and cycle fatigue characteristics.

Certain aspects of the present invention having been disclosed in connection with the foregoing variations and examples, additional variations will now be apparent to persons skilled in the art. The invention is not intended to be limited to the variations and examples specifically mentioned or presently preferred, and accordingly reference should be made to the appended claims to assess the spirit and scope of the invention in which exclusive rights are claimed. 

1. A semiconductor device comprising: a first electrically conductive layer; at least one semiconductor composition layer disposed on said first conductive layer, wherein said semiconductor composition layer comprises a solid solution of at least two perovskite materials; and a second electrically conductive layer disposed on said semiconductor layer.
 2. The semiconductor device of claim 1, wherein said device comprises at least one non-volatile memory device.
 3. The semiconductor device of claim 1, wherein said device comprises at least one resistance random access memory device.
 4. The semiconductor device of claim 1, further comprising a substrate wherein said first conductive layer is disposed on said substrate.
 5. The semiconductor device of claim 4, wherein said substrate comprises SrTiO₃.
 6. The semiconductor device of claim 4, wherein said substrate comprises at least one of platinum and silicon.
 7. The semiconductor device of claim 4, wherein said first conductive layer and said semiconductor layer maintain an epitaxial relationship with said substrate layer.
 8. The semiconductor device of claim 4, wherein said substrate layer has a crystal orientation of (100), or its crystallographic equivalent.
 9. The semiconductor device of claim 1, wherein at least one of said first conductive layer and said second conductive layer comprises SrRuO₃.
 10. A semiconductor device comprising: a first electrically conductive layer; at least one semiconductor composition layer disposed on said first conductive layer, wherein said semiconductor layer comprises at least about 75 atomic percent of an insulator oxide matrix and up to about 25 atomic percent of at least one dopant; and a second electrically conductive layer disposed on said semiconductor layer, wherein said at least one dopant has a work function equivalent to at least one of said first conductive layer and second conductive layer.
 11. The semiconductor device of claim 10, wherein said semiconductor layer comprises about 6 to about 12 atomic percent of said dopant.
 12. The semiconductor device of claim 10, wherein said semiconductor layer comprises about 5 to about 17 atomic percent of said dopant.
 13. The semiconductor device of claim 10, further comprising a substrate wherein said first conductive layer is disposed on said substrate.
 14. The semiconductor device of claim 13, wherein said substrate comprises a semiconductor.
 15. The semiconductor device of claim 13, wherein said substrate comprises SrTiO₃.
 16. The semiconductor device of claim 13, wherein said first conductive layer and said semiconductor layer maintain an epitaxial relationship with said substrate layer.
 17. The semiconductor device of claim 13, wherein said substrate layer has a crystal orientation of (100), or its crystallographic equivalent.
 18. The semiconductor device of claim 13, wherein said substrate comprises at least one of platinum and silicon.
 19. The semiconductor device of claim 10, wherein said first conductive layer comprises SrRuO₃.
 20. The semiconductor device of claim 10, further comprising at least one isolation layer.
 21. The semiconductor device of claim 10, further comprising at least one isolation layer wherein said isolation layer includes the same insulator oxide matrix as that used for the semiconductor composition layer.
 22. The semiconductor device of claim 10, wherein said device is a non-volatile memory device.
 23. The semiconductor device of claim 10, wherein said device comprises at least one resistance random access memory device. 